Method of manufacturing semiconductor device and semiconductor device

ABSTRACT

A semiconductor device includes a silicon nitride film formed above a front surface side of a semiconductor substrate, a first wiring formed above the silicon nitride film, a second wiring containing aluminum formed over the first wiring via a first insulating film, a second insulating film having an opening over the second wiring, and aluminum nitride formed over the second wiring at a bottom surface of the opening.

This Application is a Divisional Application of U.S. patent applicationSer. No. 14/592,730, which was filed on Jan. 8, 2015.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2014-005373 filed onJan. 15, 2014 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

Field of the Invention

The present invention relates to a method of manufacturing asemiconductor device and the semiconductor device and, for example, canbe suitably utilized for a method of manufacturing a semiconductordevice having a pad region, and the semiconductor device having the padregion.

Description of the Related Art

A semiconductor device having semiconductor elements, such as an MISFET,and wirings is formed by stacking over a semiconductor substrateinsulating films, such as a silicon oxide film and a silicon nitridefilm, a semiconductor film, and a conductive film. Such semiconductorelement is electrically coupled to a pad region via plural layers ofwirings. This pad region is coupled to an external terminal via a wire,a bump electrode, or the like.

For example, in Japanese Patent Laid-Open No. 2002-75996, there isdisclosed a technology of preventing contact failure of a pad by etchinga wiring layer surface using an ammonium fluoride containing liquidafter a step of etching a passivation film.

In addition, in Japanese Patent Laid-Open No. 1992-186838, there isdisclosed a technology of forming Al nitride on a surface of an Alwiring after removing Al₂O₃, which is a contamination layer of a surfaceof the wiring, using BCl₃ gas.

The present inventor is engaged in research and development of asemiconductor device having a pad region, and has earnestly examinedcharacteristic improvement thereof. In a process of the research anddevelopment, it turned out that there was a room for further improvementof the semiconductor device having the pad region.

The other problems and the new feature will become clear from thedescription of the present specification and the accompanying drawings.

SUMMARY

The following explains briefly the outline of a configuration shown inatypical embodiment disclosed in the present application.

A method of manufacturing a semiconductor device shown in typicalembodiments disclosed in the present application includes the steps of:forming an opening in an insulating film over a wiring containingaluminum, the opening exposing a part of a surface of the wiring; andforming aluminum nitride on the surface of the exposed wiring.

The semiconductor device shown in the typical embodiments disclosed inthe present application includes: the insulating film that is formedover the wiring containing aluminum and has the opening; and thealuminum nitride formed over the wiring at a bottom surface of theopening.

According to the method of manufacturing the semiconductor device shownin the typical embodiments disclosed in the present application, asemiconductor device with good characteristics can be manufactured.

In addition, according to the semiconductor device shown in the typicalembodiments disclosed in the present application, characteristicsthereof can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram showing a configuration of asemiconductor device of a first embodiment;

FIGS. 2A and 2B are cross-sectional diagrams schematically showingappearances of pad regions and back surfaces of semiconductor substratesof the semiconductor devices of the first embodiment and a comparativeexample, respectively;

FIG. 3 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment;

FIG. 4 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 3;

FIG. 5 is a schematic cross-sectional diagram of a CVD apparatus used inthe first embodiment;

FIG. 6 is a schematic cross-sectional diagram of the apparatus used inthe first embodiment;

FIG. 7 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 4;

FIG. 8 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 7;

FIG. 9 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 8;

FIG. 10 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 9;

FIG. 11 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 10;

FIG. 12 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 11;

FIG. 13 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 12;

FIG. 14 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 13;

FIG. 15 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 14;

FIG. 16 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 15;

FIG. 17 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 16;

FIG. 18 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 17;

FIG. 19 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 18;

FIG. 20 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 19;

FIG. 21 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 20;

FIG. 22 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 21;

FIG. 23 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 22;

FIG. 24 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 23;

FIG. 25 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 24;

FIG. 26 is a cross-sectional diagram showing a manufacturing step of thesemiconductor device of the first embodiment, and is the cross-sectionaldiagram showing the manufacturing step of the semiconductor devicesubsequent to FIG. 25;

FIG. 27 is a cross-sectional diagram showing a configuration of a padregion of a semiconductor device of an application of the firstembodiment;

FIG. 28 is a cross-sectional diagram showing another configuration of astacked film of the pad region;

FIG. 29 is a graph showing a relation between presence/absence of NH₃plasma treatment and the number of corrosion occurrences; and

FIG. 30 is a cross-sectional diagram showing a configuration of asemiconductor device of a second embodiment.

DETAILED DESCRIPTION

The following embodiments will be explained, divided into pluralsections or embodiments, if necessary for convenience. Except for thecase where it shows clearly in particular, they are not mutuallyunrelated and one has relationships such as a modification, anapplication, detailed explanation, and supplementary explanation of someor entire of another. In addition, in the following embodiments, whenreferring to the number of elements, etc. (including the number, anumeric value, an amount, a range, etc.), they may be not restricted tothe specific number but may be greater or smaller than the specificnumber, except for the case where they are clearly specified inparticular and where they are clearly restricted to a specific numbertheoretically.

Furthermore, in the following embodiments, an element (including anelement step etc.) is not necessarily indispensable, except for the casewhere it is clearly specified in particular and where it is consideredto be clearly indispensable from a theoretical point of view, etc.Similarly, in the following embodiments, when shape, positionrelationship, etc. of an element etc. is referred to, what resembles oris similar to the shape substantially shall be included, except for thecase where it is clearly specified in particular and where it isconsidered to be clearly not right from a theoretical point of view.This statement also applies to the number, etc. (including the number,the numeric value, the amount, the range, etc.) described above.

Hereinafter, embodiments will be explained in detail based on drawings.It is to be noted that in all the drawings for explaining theembodiments, the same or a related symbol is attached to a member havingthe same function, and that the repeated explanation thereof is omitted.In addition, when a plurality of similar members (portions) is present,a mark may be added to a symbol of a general term to thereby indicate anindividual or a particular portion in some cases. In addition, in thefollowing embodiments, explanation of the same or a similar portion isnot repeated as a principle, except for the case particularly needed.

In addition, in the drawings used in the embodiments, hatching may beomitted in order to make the drawings easy to see, even though they arecross-sectional diagrams.

In addition, in the cross-sectional diagrams, a size of each portiondoes not correspond to an actual device, and a particular portion may berepresented relatively large in some cases in order to make the drawingsintelligible.

First Embodiment

Hereinafter, a structure of a semiconductor device of the presentembodiment will be explained with reference to the drawings.

[Structure Explanation]

FIG. 1 is a cross-sectional diagram showing a configuration of thesemiconductor device of the present embodiment. The semiconductor deviceof the present embodiment has an n-channel type MISFET (NT) and ap-channel type MISFET (PT).

The n-channel type MISFET (NT) has: a gate electrode GE arranged over asubstrate S (a p-type well PW) via a gate insulating film. GI; andsource/drain regions arranged in the semiconductor substrate S (p-typewell PW) on both sides of the gate electrode GE. A side wall insulatingfilm SW including an insulating film is formed on side wall portions ofthe gate electrode GE. As the insulating film, a stacked film of asilicon oxide film SWa and a silicon nitride film SWb is used. Inaddition, the source/drain regions each have an LDD structure andinclude an n⁺ type semiconductor region NP and an n⁻ type semiconductorregion NM. The n⁻ type semiconductor region NM is formed in aself-aligned manner with respect to the side wall of the gate electrodeGE. In addition, the n⁺ type semiconductor region NP is formed in aself-aligned manner with respect to a side surface of the side wallinsulating film SW, and has a deeper junction depth and a higherimpurity concentration than the n⁻ type semiconductor region NM. Agatelength of the n-channel type MISFET (NT) is fine, for example, not morethan 150 nm.

The p-channel type MISFET (PT) has: a gate electrode GE arranged overthe semiconductor substrate S (an n-type well NW) via a gate insulatingfilm GI; and source/drain regions arranged in the semiconductorsubstrate S (n-type well NW) on both sides of the gate electrode GE. Aside wall insulating film SW including an insulating film is formed onside wall portions of the gate electrode GE. As the insulating film, astacked film of a silicon oxide film SWa and a silicon nitride film SWbis used. In addition, the source/drain regions each have an LDDstructure and include a P⁺ type semiconductor region PP and a p⁻ typesemiconductor region PM. The p⁻ type semiconductor region PM is formedin a self-aligned manner with respect to the side wall of the gateelectrode GE. In addition, the p⁺ type semiconductor region PP is formedin a self-aligned manner with respect to a side surface of the side wallinsulating film SW, and has a deeper junction depth and a higherimpurity concentration than the p⁻ type semiconductor region PM. A gatelength of the p-channel type MISFET (PT) is fine, for example, not morethan 150 nm.

In addition, an interlayer insulating film IL1 is formed over theMISFETs (NT, PT), and wirings M1 are formed over the interlayerinsulating film IL1. The source/drain regions of the MISFETs (NT, PT)and the wirings M1 are coupled to each other via plugs P1. These plugsP1 are formed in the interlayer insulating film IL1. The interlayerinsulating film IL1, for example, includes a stacked film of a siliconnitride film IL1 a located at a lower layer and a silicon oxide film IL1b located over the silicon nitride film IL1 a.

In addition, an interlayer insulating film IL2 is formed over thewirings M1, and wirings M2 are formed over the interlayer insulatingfilm IL2. These wirings M1 and M2 are coupled to each other via plugs P2formed in the interlayer insulating film IL2. In addition, an interlayerinsulating film IL3 is formed over the wirings M2, and a wiring M3 isformed over the interlayer insulating film IL3. These wirings M2 and M3are coupled to each other via a plug P3 formed in the interlayerinsulating film IL3. In addition, an interlayer insulating film IL4 isformed over the wiring M3, and a wiring M4 is formed over the interlayerinsulating film IL4. These wirings M3 and M4 are coupled to each othervia plugs P4 formed in the interlayer insulating film IL4.

A protection film PRO is formed over the wiring M4. An opening OA1 isprovided in the protection film PRO, and a part of the wiring M4 isexposed from a bottom of the opening OA1. The exposed portion of thewiring M4 is called a pad region PD1. The wiring M4 is the wiringcontaining aluminum. In other words, the wiring M4 has an aluminum film.The aluminum film described here is not limited to a pure aluminum film,and is a conductive material film (however, the conductive material filmexhibiting metallic conduction) containing aluminum as a principalcomponent. Consequently, for example, a compound film or an alloy filmof Al (aluminum) Si (silicon), and the like are also included. Inaddition, a composition ratio of Al (aluminum) in the aluminum film isdesirably larger than 50 atom % (i.e., the aluminum film is Al-rich).

In the semiconductor device of the present embodiment, the wiring M4 isthe top-layer wiring, desired wire connection of a semiconductor element(for example, the above-described MISFET) is made by the wirings (M1 toM4), and desired operation can be performed. Consequently, utilizing thepad region PD1, which is the exposed portion of the wiring (top-layerwiring) M4, can be performed a test (a test step) of whether or not thesemiconductor device performs the desired operation.

In addition, as will be mentioned later, a projection electrode (a bumpelectrode) BP including a conductive member is formed over the padregion PD1. In addition, a bonding wire including a conductive membermay be connected to over the pad region PD1 (refer to FIG. 26).

Here, in the present embodiment, an aluminum nitride film M4 e is formedon the pad region PD1 (an exposed surface) of the wiring (top-layerwiring) M4 containing aluminum, and thereby corrosion of the wiring M4is prevented. The corrosion prevention will be explained in detailhereinafter.

FIGS. 2A and 2B are diagrams schematically showing appearances of padregions and back surfaces of semiconductor substrates of semiconductordevices of the present embodiment and a comparative example,respectively. FIG. 2A shows a case of the semiconductor device of thepresent embodiment, and FIG. 2B shows a case of the semiconductor deviceof the comparative example.

As shown in FIG. 2B, the wiring M4 over the plugs P4 has: atitanium/titanium nitride film M4 a; an aluminum film M4 b; and atitanium film M4 c. The titanium/titanium nitride film M4 a is a stackedfilm of a titanium film and a titanium nitride film formed thereover.The protection film PRO is formed over the wiring M4, and a main surfaceof the aluminum film M4 b is exposed from a bottom of the opening OA1(pad region PD1) in the protection film PRO. In other words, theprotection film PRO and the titanium film M4 c over the pad region PD1over the wiring M4 are removed, and the aluminum film M4 b is exposed.In the comparative example, foreign substances PA have been generatedover the exposed portion of the aluminum film M4 b.

Here, a silicon nitride film (SiN) and a silicon oxide film (SiO₂) areformed on the back surface of the semiconductor substrate S. It is to benoted that in FIG. 2B, omitted is description of the wirings, the plugs,and the MISFETs (NT, PT) in the lower layers than the plugs P4, whichare formed in the interlayer insulating film IL.

As shown in FIG. 2A, in the present embodiment, the wiring M4 over theplugs P4 has: the titanium/titanium nitride film M4 a; the aluminum filmM4 b; and the titanium film M4 c. The protection film PRO is formed overthe wiring M4, and the main surface of the aluminum film M4 b is exposedfrom the bottom of the opening OA1 (pad region PD1) in the protectionfilm PRO. In other words, the protection film PRO and the titanium filmM4 c over the pad region PD1 over the wiring M4 are removed, and thealuminum film M4 b is exposed. Here, the aluminum nitride film M4 e isformed over the aluminum film M4 b. Also here, a silicon nitride film(SiN) and a silicon oxide film (SiO₂) are formed on the back surface ofthe semiconductor substrate S. These insulating films are, as will bementioned later, formed by using a batch-type film formation apparatusin a manufacturing step of the semiconductor device. It is to be notedthat in FIG. 2A, omitted is description of the wirings, the plugs, andthe MISFETs (NT, PT) in the lower layers than the plugs P4, which areformed in the interlayer insulating film IL.

According to examination of the present inventors, when the aluminumfilm M4 b is exposed from the pad region PD1 as in the semiconductordevice of the comparative example, the aluminum film M4 b exposed fromthe pad region PD1 corrodes. More specifically, undesired reactants (theforeign substances PA) are generated on a surface of the aluminum filmM4 b exposed from the pad region PD1 (refer to FIG. 2B).

Additionally, it turned out that such reactants were generated more inthe semiconductor device in which a film had been formed on the backsurface of the semiconductor substrate S than in the semiconductordevice in which the film had not been formed on the back surface of thesemiconductor substrate S. Furthermore, it turned out that a generationamount of NH₄ ⁺ was large in the semiconductor device in which the filmhad been formed on the back surface of the semiconductor substrate S ascompared with the semiconductor device in which the film had not beenformed on the back surface of the semiconductor substrate S.

As a result of these, it is considered that the silicon nitride filmformed on the back surface of the semiconductor substrate is concernedwith the undesired reactants (foreign substances PA) formed on thesurface of the aluminum film M4 b.

Namely, it turned out that the generation amount of NH₄ ⁺ increased dueto the silicon nitride film (SiN) when the silicon nitride film (SiN) onthe back surface of the semiconductor substrate S had been formed.Al(OH)₃ deposits as foreign substances due to reaction of the NH₄ ⁺ andAl (an Al ion).

Formation reaction of Al(OH)₃ is shown below.

2Al=2Al₃ ⁺+6e ⁻  (Chemical formula 1)

6NH₃+6H₂O=6NH₄ ⁺+6OH⁻  (Chemical formula 2)

2Al₃ ⁺+6HO⁻=2Al(OH)₃↓  (Chemical formula 3)

6NH₄ ⁺+6e=6NH₃+3H₂↑  (Chemical formula 4)

When such foreign substances (Al(OH)₃) are generated, the conductivemembers (the bump electrode, the bonding wire) cannot be accuratelyformed over the pad region PD1, and the semiconductor device becomesdefective.

Furthermore, according to the examination of the present inventors, itwas proved that the silicon nitride film formed on the back surface ofthe semiconductor substrate, even in a case where it was covered withthe silicon oxide film or the like, passes through the silicon oxidefilm to generate NH₄ ⁺.

Consequently, it was proved that once the silicon nitride film wasformed on the back surface of the semiconductor substrate in themanufacturing step of the semiconductor device, the foreign substances(Al(OH)₃) were generated due to the silicon nitride film.

In addition, after a formation step of the pad region PD1, subsequentsteps, such as an inspection step and a bonding step, are standing by.There is a case of requiring time before the inspection step and thebonding step in the manufacturing steps of the semiconductor device. Forexample, the semiconductor device may be stored within a FOUP (alsocalled a substrate storage container or a substrate accommodationcontainer) for not less than a week. In a case where a storage period islong as described above, the above-described formation reaction ofAl(OH)₃ proceeds. In addition, the inspection step and the bonding stepmay be performed at a location different from a previous manufacturingline, and in that case, a storage period including a transport step ofthe FOUP may become long. In this case as well, the above-describedformation reaction of Al(OH)₃ proceeds.

In contrast with this, according to the present embodiment, since thealuminum nitride film M4 e is provided over the pad region PD1, theformation reaction of the foreign substances can be prevented in the padregion PD1. Particularly, even in the case of requiring time before theinspection step and the bonding step after the formation step of the padregion PD1, the formation reaction of the foreign substances can beprevented in the pad region PD1.

Furthermore, since the aluminum nitride film M4 e over the pad regionPD1 is a thin film (not more than 10 nm), it is easily broken at thetime of a pressure bonding step of the conductive members (the bumpelectrode, the bonding wire) over the pad region PD1, and electricalconduction of the conductive members and the pad region PD1 (wiring M4)can be achieved.

[Manufacturing Method Explanation]

Next, a method of manufacturing the semiconductor device of the presentembodiment will be explained with reference to FIGS. 3 to 26. FIGS. 3 to26 (except for FIGS. 5 and 6) are cross-sectional diagrams showingmanufacturing steps of the semiconductor device of the presentembodiment.

As shown in FIG. 3, as the semiconductor substrate (a wafer) S, forexample, prepared is a silicon substrate including p-type single crystalsilicon having a specific resistance of approximately 1 to 10 Ωcm. It isto be noted that a semiconductor substrate S other than the siliconsubstrate may be used.

Next, an element isolation region STI is formed on a main surface of thesemiconductor substrate S. For example, an element isolation groove isformed in the semiconductor substrate S, an insulating film, such as asilicon oxide film, is buried inside the element isolation groove, andthereby the element isolation region STI is formed. It is to be notedthat the element isolation region may be formed using a LOCOS (LocalOxidation of Silicon) method.

Next, the p-type well PW is formed in a formation region of then-channel type MISFET (NT) of the semiconductor substrate S, and then-type well NW is formed in a formation region of the p-channel typeMISFET (PT) thereof.

For example, as shown in FIG. 4, the formation region of the p-channeltype MISFET (PT) is covered with a mask film MN, a p-type impurity (suchas boron (B)) is ion-implanted, and thereby the p-type well PW is formed(FIG. 7). The mask film MN, for example, includes a silicon oxide film,and can be formed by a CVD (Chemical Vapor Deposition) method. After thesilicon oxide film is formed over a whole surface of the semiconductorsubstrate S as the mask film MN, patterning is performed using aphotolithography technology and an etching technology, and thereby themask film MN other than the formation region of the p-channel typeMISFET (PT) is removed.

Here, it is possible to simultaneously form the mask films MN (siliconoxide films) with respect to the plurality of semiconductor substratesS. FIG. 5 is a schematic cross-sectional diagram of a CVD apparatus usedin the present embodiment. In a CVD apparatus 100 shown in FIG. 5, theplurality of semiconductor substrates (wafers) S is stored inside achamber (a treatment chamber, a furnace) 100 a, they are exposed tosource gas introduced from a gas introduction hole 100 b, and the maskfilms MN (silicon oxide films) are formed over the whole surfaces of thesemiconductor substrates S. At this time, since outer peripheralportions of the back surfaces of the semiconductor substrates S aresupported (held) by support portions, and most of the back surfaces areexposed from the support portions, the mask films MN (silicon oxidefilms) are formed not only on front surface sides (upper sides in FIG.5) of the semiconductor substrates S but on back surface sides (lowersides in FIG. 5) thereof (refer to FIG. 4). An apparatus thatsimultaneously treats the plurality of semiconductor substrates S asdescribed above may be called a batch-type apparatus.

In contrast with this, an apparatus shown in FIG. 6 is the apparatusthat treats the semiconductor substrate S one by one. FIG. 6 is aschematic cross-sectional diagram of the apparatus used in the presentembodiment. Such apparatus may be called a single-wafer type apparatus.For example, when a film is formed by such a single-wafer type CVDapparatus, the semiconductor substrate (wafer) S is mounted at a stage(a substrate mounting base) 100 c in the chamber (treatment chamber) 100a, and the film is formed over the whole surface of the semiconductorsubstrate S by source gas introduced from a gas introduction hole (notshown). In a case of treatment using such single-wafer type CVDapparatus, since the back surface of the semiconductor substrate S is incontact with the stage 100 c, the film is not formed on the back surfaceside of the semiconductor substrate S. In addition, the “single-wafertype” apparatus shown in FIG. 6 is used not only for a film formationapparatus, such as the CVD apparatus, but for a treatment apparatus,such as a dry etching apparatus.

Consequently, as mentioned above, when the mask film MN (silicon oxidefilm) is formed by the batch-type apparatus, the mask film MN is formedalso on the back surface side of the semiconductor substrate S (refer toFIG. 4). Additionally, when etching of the mask film MN is performed bya single-wafer type etching apparatus, the mask film MN on the backsurface side of the semiconductor substrate S becomes a state of notbeing removed but remaining (refer to FIG. 4). It is to be noted thatwhen not clearly specified in an after-mentioned treatment step,treatment shall be performed by the single-wafer type apparatus.

After the p-type well PW is formed by using the mask film MN as a mask,as shown in FIG. 8, the formation region of the n-channel type MISFET(NT) is covered with a mask film MP including a silicon oxide film, ann-type impurity (arsenic (As) or phosphorus (P)) is ion-implanted, andthereby the n-type well NW is formed. The mask film MP formed at thistime is, similarly to the film MN, formed also on the back surface sideof the semiconductor substrate S. Consequently, a stacked film of themask film MN and the mask film MP is formed on the back surface of thesemiconductor substrate S from the substrate side. Next, heat treatmentfor activating the implanted impurity, and the mask film MP (siliconoxide film) is removed by dry etching.

Next, as shown in FIG. 9, the gate electrode GE is formed on the mainsurface (main surfaces of the p-type well PW and the n-type well NW) ofthe semiconductor substrate S via the gate insulating film GI. Forexample, the gate insulating film GI including the silicon oxide film isformed by thermally oxidizing the main surface (main surfaces of thep-type well PW and the n-type well NW) of the semiconductor substrate S.As the gate insulating film GI, a silicon nitride film and a siliconoxynitride film may be used in addition to the silicon oxide film. Inaddition, a high dielectric constant film (a so-called high-k film) maybe used as the gate insulating film GI. In addition, the gate insulatingfilm GI may be formed using another film formation method, such as theCVD method, in addition to a thermal oxidation method.

Next, a silicon film is formed as a conductive film (a conductor film).As the silicon film, for example, a polycrystalline silicon film isformed using the CVD method or the like. The gate electrode GE is formedby patterning the polycrystalline silicon film using thephotolithography technology and the etching technology. It is to benoted that an impurity may be implanted into a material (thepolycrystalline silicon film here) that configures the gate electrode GEaccording to a characteristic of each MISFET (NT, PT).

Next, source/drain regions are formed in the semiconductor substrate S(the p-type well PW, the n-type well NW) of both sides of each gateelectrode GE.

First, the n-type impurity, such as arsenic (As) or phosphorus (P), isimplanted into the p-type well PW of the both sides of the gateelectrode GE, and the n⁻ type semiconductor regions NM are formed (FIG.9). The n⁻ type semiconductor regions NM are formed on the side walls ofthe gate electrode GE in a self-aligned manner. In addition, the p-typeimpurity, such as boron (B), is implanted into the n-type well NW of theboth sides of the gate electrode GE, and the p⁻ type semiconductorregions PM are formed (FIG. 9). The p⁻ type semiconductor regions PM areformed on the side walls of the gate electrode GE in a self-alignedmanner.

Next, the side wall insulating film (a side wall film) SW is formed onthe side wall portions of the gate electrode GE. For example, as shownin FIG. 10, an insulating film that configures the side wall insulatingfilm SW is formed over the whole main surface of the semiconductorsubstrate S. Here, the stacked film of the silicon oxide film SWa andthe silicon nitride film SWb is used. The silicon oxide film SWa isformed over the whole main surface of the semiconductor substrate S, forexample, using a batch-type CVD apparatus. Next, the silicon nitridefilm SWb is formed over the silicon oxide film SWa, for example, using abatch-type low-pressure CVD apparatus. As a result, the stacked film ofthe silicon oxide film SWa and the silicon nitride film SWb is formedover the whole main surface of the semiconductor substrate S. At thistime, the stacked film of the silicon oxide film SWa and the siliconnitride film SWb is formed also on the back surface of the semiconductorsubstrate S similarly to the cases of the above-mentioned mask films MPand MN. Consequently, the mask film MN, the mask film MP, and thestacked film of the silicon oxide film SWa and the silicon nitride filmSWb are formed on the back surface of the semiconductor substrate S fromthe substrate side. It is to be noted that as the side wall insulatingfilm SW, an insulating film, such as a single-layer silicon oxide filmand a single-layer silicon nitride film, may be used in addition to thestacked film of the silicon oxide film SWa and the silicon nitride filmSWb.

Next, as shown in FIG. 11, the side wall insulating film SW is formed onthe side wall portions of the gate electrode GE by etching back thestacked film of the silicon oxide film SWa and the silicon nitride filmSWb. The etch back of the stacked film is performed by a single-wafertype etching apparatus. Consequently, the stacked film of the siliconoxide film SWa and the silicon nitride film SWb on the back surface sideof the semiconductor substrate S becomes a state of remaining withoutbeing removed.

Next, as shown in FIG. 12, the n-type impurity, such as arsenic (As) orphosphorus (P), is implanted into the p-type well PW on both sides of acomposite body of the gate electrode GE and the side wall insulatingfilm SW, and the n⁺ type semiconductor regions NP are formed. The n⁺type semiconductor regions NP are formed on the side walls of the sidewall insulating film SW in a self-aligned manner. The n⁺ typesemiconductor regions NP are formed as semiconductor regions that have ahigher impurity concentration and a deeper junction depth than the n⁻type semiconductor regions NM. In addition, the p-type impurity, such asboron (B), is implanted into the n-type well NW of the both sides of thecomposite body of the gate electrode GE and the side wall insulatingfilm SW, and the p⁺ type semiconductor regions PP are formed. The p⁺type semiconductor regions PP are formed on the side walls of the sidewall insulating film SW in a self-aligned manner. The p⁺ typesemiconductor regions PP are formed as semiconductor regions that have ahigher impurity concentration and a deeper junction depth than the p⁻type semiconductor regions PM. Next, heat treatment for activating theimplanted impurity is performed. As a result, the source/drain regionsof the LDD structure including the n⁻ type semiconductor region NM andthe n⁺ type semiconductor region NP are formed in the p-type well PW ofthe both sides of the gate electrode GE, and the source/drain regions ofthe LDD structure including the p⁻ type semiconductor region PM and thep⁺ type semiconductor region PP are formed in the n-type well NW of theboth sides of the gate electrode GE.

According to the above steps, the n-channel type MISFET (NT) is formedon a main surface of the p-type well PW, and the p-channel type MISFET(PT) is formed on a main surface of the n-type well NW.

Next, a metal silicide film SIL is formed at upper parts of the gateelectrode GE, the n⁺ type semiconductor region NP, and the P⁺ typesemiconductor region PP, respectively using a salicide technology.

First, a silicon oxide film is formed as a silicide mask SM at a region(not shown) where the metal silicide film SIL is not formed, forexample, using the batch-type CVD apparatus (refer to FIG. 13). At thistime, similarly to the above-mentioned cases of the mask films MP andMN, and the stacked film of the silicon oxide film SWa and the siliconnitride film SWb, the silicide mask SM (silicon oxide film) is formedalso on the back surface of the semiconductor substrate S. Consequently,the mask film MN, the mask film MP, the stacked film of the siliconoxide film SWa and the silicon nitride film SWb, and the silicide maskSM are formed on the back surface of the semiconductor substrate S fromthe substrate side.

Next, the silicide mask SM (silicon oxide film) over the n-channel typeMISFET (NT) and the p-channel type MISFET (PT) is removed using thephotolithography technology and the etching technology (refer to FIG.13).

Next, as shown in FIG. 13, a metal film M is formed over the wholesurface of the semiconductor substrate S, heat treatment is appliedthereto, and thereby the gate electrode GE, the n⁺ type semiconductorregion NP, and the P⁺ type semiconductor region PP are made to reactwith the metal film M. As a result, the metal silicide film SIL isformed at the upper parts of the gate electrode GE, the n⁺ typesemiconductor region NP, and the P⁺ type semiconductor region PP,respectively. The above-described metal film, for example, includes acobalt (Co) film or a nickel (Ni) film, and can be formed using asputtering method or the like. Next, the unreacted metal film M isremoved (refer to FIG. 14). It is to be noted that a formation step ofthe metal silicide film SIL may be skipped.

Next, the insulating film (interlayer insulating film) IL1 is formedover the n-channel type MISFET (NT) and the p-channel type MISFET (PT).First, as shown in FIG. 15, the silicon nitride film IL1 a is formed soas to cover upper sides of the source/drain regions of the MISFETs (NT,PT) and the gate electrode GE. The silicon nitride film IL1 a is formedusing the batch-type CVD apparatus. At this time, similarly to theabove-mentioned mask films MP, MN, and the like, the silicon nitridefilm IL1 a is formed also on the back surface of the semiconductorsubstrate S. Consequently, the mask film MN, the mask film MP, thestacked film of the silicon oxide film SWa and the silicon nitride filmSWb, the silicide mask SM, and the silicon nitride film IL1 a are formedon the back surface of the semiconductor substrate S from the substrateside.

Next, as shown in FIG. 16, the silicon oxide film IL1 b formed thickerthan the silicon nitride film IL1 a is formed over the silicon nitridefilm IL1 a using the CVD method or the like. As a result, the interlayerinsulating film IL1 including a stacked film of the silicon nitride filmIL1 a and the silicon oxide film IL1 b can be formed. After formation ofthe interlayer insulating film IL1, an upper surface of the interlayerinsulating film IL1 is planarized using a CMP method or the like ifneeded.

Next, as shown in FIG. 17, contact holes are formed in the interlayerinsulating film IL1 by selectively removing the interlayer insulatingfilm IL1 using the photolithography technology and the etchingtechnology. At this time, utilizing an etching selection ratio of thesilicon nitride film IL1 a and the silicon oxide film IL1 b, first, thesilicon oxide film IL1 b is etched, the exposed silicon nitride film IL1a is further etched, and thereby the contact holes can be formedaccurately.

Next, a stacked film of a barrier conductor film (not shown) and a mainconductor film is formed over the interlayer insulating film IL1including insides of the contact holes. Next, the plugs P1 are formed byremoving the unnecessary main conductor film and barrier conductor filmover the interlayer insulating film IL1 by means of the CMP method or anetch-back method. These plugs P1 are, for example, formed at the upperparts of the n⁺ type semiconductor region NP and the P⁺ typesemiconductor region PP via the metal silicide film SIL. In addition,the plugs P1 may be formed at the upper part of the gate electrode GE.It is to be noted that, for example, a titanium film, a titanium nitridefilm, or a stacked film thereof can be used as the barrier conductorfilm. In addition, a tungsten film or the like can be used as the mainconductor film.

Next, the wirings M1 including the conductive film are formed over theinterlayer insulating film IL1 in which the plugs P1 have been buried.For example, a stacked film including a titanium/titanium nitride film,an aluminum film, and a titanium/titanium nitride film is sequentiallydeposited over the interlayer insulating film IL1 and the plugs P1 asthe conductive film using the sputtering method or the like. The stackedfilm of the titanium/titanium nitride film is also called the barrierconductor film. Next, the wirings M1 are formed over the plugs P1 bypatterning the above-described stacked film using the photolithographytechnology and the etching technology.

The above-described aluminum film for forming the wirings M1 is notlimited to a pure aluminum film, and can be used a conductive materialfilm (however, the conductive material film exhibiting metallicconduction) containing aluminum as a principal component. For example, acompound film or an alloy film of Al (aluminum) and Si (silicon) can beused. In addition, a composition ratio of Al (aluminum) in the aluminumfilm is desirably larger than 50 atom % (i.e., the aluminum film is theAl-rich one). The same applies not only to the above-described aluminumfilm for forming the wirings M1 but to the aluminum films for formingthe wirings M2 to M3.

Next, as shown in FIG. 18, the interlayer insulating film IL2 is formedover the wirings M1. For example, a silicon oxide film is deposited overthe wirings M1 by the CVD method or the like.

Next, contact holes are formed in the interlayer insulating film IL2 byselectively removing the interlayer insulating film IL2 using thephotolithography technology and the etching technology. Next, the plugsP2 are formed in the interlayer insulating film IL2 by burying aconductive film inside the contact holes. These plugs P2 can be formedsimilarly to the plugs P1. Next, the wirings M2 including the conductivefilm are formed over the plugs P2. For example, a stacked film includinga titanium/titanium nitride film, an aluminum film, and atitanium/titanium nitride film is sequentially deposited over theinterlayer insulating film IL2 and the plugs P2 as the conductive filmusing the sputtering method or the like. Next, the wirings M2 are formedover the above-described plugs P2 by patterning the above-describedstacked film using the photolithography technology and the etchingtechnology.

Next, as shown in FIG. 19, the interlayer insulating film IL3 is formedover the wirings M2. For example, a silicon oxide film is deposited overthe wirings M2 by the CVD method or the like. Next, a contact hole isformed in the interlayer insulating film IL3 by selectively removing theinterlayer insulating film IL3 using the photolithography technology andthe etching technology. Next, the plug P3 is formed in the interlayerinsulating film IL3 by burying a conductive film inside the contacthole. This plug P3 can be formed similarly to the plugs P1. Next, thewiring M3 including the conductive film is formed over the plug P3. Forexample, a stacked film including a titanium/titanium nitride film, analuminum film, and a titanium/titanium nitride film is sequentiallydeposited over the interlayer insulating film IL3 and the plug P3 as theconductive film using the sputtering method or the like. Next, thewiring M3 is formed over the above-described plug P3 by patterning theabove-described stacked film using the photolithography technology andthe etching technology.

Next, as shown in FIG. 20, the interlayer insulating film IL4 is formedover the wiring M3. For example, a silicon oxide film is deposited overthe wiring M3 by the CVD method or the like. Next, contact holes areformed in the interlayer insulating film IL4 by selectively removing theinterlayer insulating film IL4 using the photolithography technology andthe etching technology. Next, the plugs P4 are formed in the interlayerinsulating film IL4 by burying a conductive film inside the contactholes. These plugs P4 can be formed similarly to the plugs P1.

Next, as shown in FIG. 21, the wiring M4 including the conductive filmis formed over the plugs P4. For example, a stacked film including thetitanium/titanium nitride film M4 a, the aluminum film M4 b, and thetitanium film M4 c is sequentially deposited over the interlayerinsulating film IL4 and the plugs P4 as the conductive film using thesputtering method or the like. Next, the wiring M4 is formed over theabove-described plugs P4 by patterning the above-described stacked filmusing the photolithography technology and the etching technology. It isto be noted that at the time of the patterning of the wiring M4, forexample, a silicon oxynitride film may be formed over the wiring M4 asan anti-reflection film. The silicon oxynitride film may be removed ormay be made to remain over the wiring M4 after patterning of the wiringM4.

Next, as shown in FIG. 22, passivation treatment (oxidation treatment)of side surfaces (side surfaces of the aluminum film M4 b) of the wiringM4 is performed. For example, an aluminum oxide film (an Al₂O₃ film) M4d is formed on the side surfaces (side surfaces of the aluminum film M4b) of the wiring M4 by performing oxygen plasma treatment on the wiringM4. For example, treatment is performed for 120 seconds under acondition of stage temperature: 250° C.; high frequency power: 2000 W;pressure inside the treatment chamber: 100 Pa; and O₂ gas flow rate:7000 mL/min (sccm). According to such treatment, the aluminum oxide filmhaving a film thickness of approximately 1 to 5 nm can be formed on theside surfaces of the wiring M4. It is to be noted that treatment usingozone (O₃) can also be performed for passivation treatment (oxidationtreatment) in addition to the treatment using oxygen.

Next, as shown in FIG. 23, the protection film PRO is formed over thewiring M4. For example, a silicon nitride film PROa is deposited overthe interlayer insulating film IL4 including a top of the wiring M4 bythe CVD method or the like. and further, a silicon oxide film PROb isdeposited over the silicon nitride film PROa by the CVD method or thelike.

Next, as shown in FIG. 24, the opening OA1 is formed by removing theprotection film PRO over the pad region PD1 of the wiring M4 (aluminumfilm M4 b). For example, a photoresist film having an opening in theformation region of the opening OA1 is formed over the protection filmPRO, and the protection film PRO is etched by using the photoresist filmas a mask. When the anti-reflection film remains, the film is alsoetched. Next, the exposed titanium film M4 c is further etched. As aresult, the aluminum film M4 b of the pad region PD1 is exposed. Inother words, the pad region PD1 of the aluminum film M4 b is exposed tothe bottom surface of the opening OA1.

Next, as shown in FIG. 25, the aluminum nitride film (AlN film) M4 e isformed by nitriding the pad region PD1 of the aluminum film M4 b. Forexample, ammonia (NH₃) plasma treatment is performed. For example,treatment is performed for 20 seconds under a condition of stagetemperature: 400° C.; high frequency power: 270 W; pressure inside thetreatment chamber: 660 Pa; and NH₃ gas flow rate: 145 mL/min (sccm). Itis to be noted that in nitriding treatment, plasma treatment usingnitrogen compound gas, such as nitrogen (N₂) and ammonia (NH₃), isperformed.

According to such treatment, the aluminum nitride film (AlN film) havinga film thickness of approximately 3 to 6 nm can be formed on a surfaceof the pad region PD1. The film thickness of the aluminum nitride film(AlN film) is preferably set to be less than 10 nm.

Next, utilizing the pad region PD1, performed is a test of whether ornot the semiconductor device performs desired operation. For example, aprobe needle is stuck into the pad region PD1, a predeterminedelectrical signal is applied thereto, and performed is test of whetheror not the semiconductor device performs desired operation. At thistime, since the film thickness of the aluminum nitride film (AlN film)is several nanometers, the aluminum nitride film can be easily brokenthrough by the probe needle, and does not interfere with electricalconduction of the probe needle and the pad region PD1. A probe mark isformed in the pad region PD1 due to this test step.

After that, back grinding of the semiconductor substrate S is performed,the semiconductor substrate S is reduced in film thickness, and is cut(diced) to be divided into a plurality of semiconductor chips (dividedinto individual pieces). As a result, the semiconductor chip is obtainedfrom each chip region of the semiconductor substrate S (semiconductorwafer).

Next, as shown in FIG. 26, the projection electrode (bump electrode) BPincluding the conductive member is formed over the pad region PD1(bonding step). The conductive member, for example, includes gold or analloy containing gold. For example, a gold ball is formed at a tip of awire including gold by an electric torch, and the wire connected to thegold ball is cut while crimping the gold ball to the pad region PD1.After this, a gold bump is mounted over an external terminal (a wiring,a lead) formed on a wiring substrate or the like, they are electricallycoupled to each other, and thereby the semiconductor device (chip) canbe mounted. In addition, electrical coupling of the pad region PD1 andthe wiring (lead) may be performed by a bonding wire. In this case, forexample, the gold ball is formed at one end of the wire including goldby the electric torch and is crimped to the pad region PD1, and multipleends of the wire connected to the gold ball are crimped to the wiring(lead).

As described above, the conductive member (the bump electrode, thebonding wire) electrically coupled to the external terminal is fixedover the pad region PD1 by applying pressure, and thereby the aluminumnitride film M4 e is cracked (broken), and electrical coupling of thewiring M4 and the conductive member (BP) can be achieved via cracks ofthe aluminum nitride film M4 e.

As explained above in detail, according to the present embodiment, sincethe aluminum nitride film M4 e is provided over the pad region PD1,formation reaction of foreign substances in the pad region PD1 can beprevented also in the case where the silicon nitride film (SWb, IL1 a)is formed on the back surface of the semiconductor substrate.Particularly, after the formation step of the pad region PD1, also in acase where time is required by the inspection step and the bonding step,the silicon nitride film is formed on the back surface of thesemiconductor substrate, and where a state of the exposure of the padregion PD1 continues for a long period of time, formation reaction offoreign substances can be effectively prevented.

Particularly, since an influence of the film formed on the back surfacebecomes larger along with enlargement in diameter of the semiconductorsubstrate (wafer), application of the present embodiment is effective,for example, when a semiconductor substrate (wafer) having a diameternot less than 300 mm is used.

It is to be noted that although in the above-described manufacturingsteps, the formation step of the silicon oxide film SWa and theformation step of the silicon nitride film IL1 a have been exemplifiedas the step in which the silicon nitride film is formed on the backsurface of the semiconductor substrate, the present invention is notlimited to these. A silicon nitride film may be used for anothercomponent part of the semiconductor device, and it is needless to saythat in a formation step of the silicon nitride film, the siliconnitride film can be formed on the back surface of the semiconductorsubstrate in some cases. In addition, a silicon nitride film may be usedas a mask film formed in various treatment steps (for example, an ionimplantation step), it is needless to say that in a formation step ofthe silicon nitride film, the silicon nitride film can be formed on theback surface of the semiconductor substrate in some cases.

(Application)

Although in the above-described manufacturing steps, nitriding treatmentof the pad region PD1 of the aluminum film M4 b is performed after theopening OA1 is formed, the nitriding treatment may be performed afterpassivation treatment (oxidation treatment) is performed on the padregion PD1 of the aluminum film M4 b. It is to be noted that since anapplication is similar to the first embodiment except for theconfiguration over the pad region PD1 of the aluminum film M4 b,detailed explanation thereof is omitted.

FIG. 27 is a cross-sectional diagram showing a configuration of a padregion of a semiconductor device of the application of the presentembodiment. As shown in FIG. 27, in the present application, the wiringM4 has: the titanium/titanium nitride film M4 a; the aluminum film M4 b;and the titanium film M4 c. The aluminum oxide film (Al₂O₃ film) M4 d isformed on the side walls of the wiring M4.

In addition, the protection film PRO is formed over the wiring M4, and astacked film of an aluminum oxide film M4 f and the aluminum nitridefilm M4 e is provided in the opening OA1 (pad region PD1) in theprotection film PRO. In other words, in the opening OA1 (pad region PD1)in the protection film PRO, the aluminum oxide film M4 f is formed overthe aluminum film M4 b and further, the aluminum nitride film M4 e isformed over the aluminum oxide film M4 f.

As described above, also when the stacked film of the aluminum oxidefilm M4 f and the aluminum nitride film M4 e is provided over the padregion PD1, formation reaction of foreign substances can be prevented inthe pad region PD1.

Next, there will be explained a step of forming the stacked film of thealuminum oxide film M4 f and the aluminum nitride film M4 e over the padregion PD1.

First, as explained with reference to FIG. 24, the opening OA1 is formedby removing the protection film PRO over the pad region PD1 of thewiring M4 (aluminum film M4 b) and further, the exposed titanium film M4c is etched. As a result, the aluminum film M4 b of the pad region PD1is exposed.

Next, the aluminum oxide film (Al₂O₃ film) M4 f is formed by oxidizingthe pad region PD1 of the aluminum film M4 b (refer to FIG. 27). Forexample, oxygen plasma treatment is performed for 120 seconds under acondition of stage temperature: 250° C.; high frequency power: 2000 W;pressure inside the treatment chamber: 100 Pa; and O₂ gas flow rate:7000 mL/min (sccm).

Next, the aluminum nitride film (AlN film) is formed by nitriding thepad region PD1 of the aluminum film M4 b. For example, NH₃ plasmatreatment is performed for 20 seconds under a condition of stagetemperature: 400° C.; high frequency power: 270 W; pressure inside thetreatment chamber: 660 Pa; and NH₃ gas flow rate: 145 mL/min (sccm).

In this NH₃ plasma treatment, after the aluminum oxide film (Al₂O₃ film)M4 f is reduced, and the aluminum oxide film is converted into aluminum,an aluminum nitride film can be formed. As a result, the stacked film ofthe aluminum oxide film M4 f and the aluminum nitride film M4 e can beformed over the pad region PD1.

It is to be noted that depending on a film thickness of the aluminumoxide film M4 f, all of it may become the aluminum nitride film M4 e.

In addition, the aluminum oxide film M4 f is hard to form as a uniformfilm, and it may be a discontinuous film having pinholes in some cases.FIG. 28 is a cross-sectional diagram showing another configuration of astacked film of the pad region. As shown in FIG. 28, the aluminumnitride film M4 e may be formed so as to fill regions (pinholes) PINwhere the aluminum oxide film M4 f has not been formed. In this case,for example, N₂ plasma treatment is performed. Since there is noreduction action in the N₂ plasma treatment, the aluminum nitride filmM4 e is formed in the regions (pinholes) PIN where the aluminum oxidefilm M4 f has not been formed.

In such a case as well, the pad region PD1 is covered with the aluminumoxide film M4 f or the aluminum nitride film M4 e, and formationreaction of foreign substances can be prevented in the pad region PD1.As a matter of course, NH₃ plasma treatment may be performed, and thealuminum nitride film M4 e may be formed on the whole pad region PD1including the regions (pinholes) PIN where the aluminum oxide film M4 fhas not been formed.

As described above, both of the oxidation treatment and the nitridingtreatment may be applied to the pad region PD1. However, since thealuminum oxide film M4 f and the aluminum nitride film M4 e that areformed are the thin films having thicknesses not more than 5 nm and lessthan 10 nm, respectively, it is considered that a stacked state of thefilms can have various modes.

Formation of the films in the stacked states shown in FIGS. 27 and 28can be confirmed by detecting component elements of the aluminum oxidefilm M4 f and the aluminum nitride film M4 e by means of Auger electronspectroscopy analysis and the like.

It is to be noted that since the aluminum oxide film M4 f easily becomesthe discontinuous film having the pinholes as mentioned above, it is notpreferable to cover the pad region PD1 with a single layer of thealuminum oxide film M4 f. As shown in FIGS. 27 and 28, formationreaction of foreign substances can be effectively prevented in the padregion PD1 by forming the aluminum nitride film M4 e together with thealuminum oxide film M4 f.

Experimental Example

FIG. 29 is a graph showing a relation between presence/absence of NH₃plasma treatment and the number of corrosion occurrences. A horizontalaxis indicates a wafer number, and a vertical axis indicates the numberof corrosion occurrences [number]. Visual inspection test was performedon twenty-four wafers (semiconductor substrates) left (stored) for eightdays, and twenty-four wafers (semiconductor substrates) left (stored)for twelve days in a state where silicon nitride films were formed onback surfaces of the semiconductor substrates, and where the pad regionsPD1 were exposed.

When NH₃ plasma treatment was not performed (rhombus marks), the numberof corrosion occurrences increased from two to three as a leaving periodbecomes longer. Namely, the number of corrosion occurrences increasedfrom two to three as the leaving period became longer. In contrast withthis, when NH₃ plasma treatment was performed (square marks), the numberof corrosion occurrences was zero regardless of the leaving period.Namely, the number of corrosion occurrences in the case where NH₃ plasmatreatment was performed (square marks) was less than that in the casewhere NH₃ plasma treatment was not performed (rhombus marks), and thenumber of corrosion occurrences remained less even though the leavingperiod became longer.

As described above, a preventive effect on corrosion (formation reactionof foreign substances) by the aluminum nitride film M4 e over the padregion PD1 could be confirmed.

Second Embodiment

Although in the first embodiment, the projection electrode (bumpelectrode) BP including the conductive member is formed over the padregion PD1 (refer to FIG. 26), a rewiring may be provided over the padregion PD1, and the projection electrode BP including the conductivemember may be provided over the rewiring.

FIG. 30 is a cross-sectional diagram showing a configuration of asemiconductor device of the present embodiment. Since configurations oflayers lower than the wiring M4 are similar to the case of the firstembodiment, detailed explanation thereof is omitted.

As shown in FIG. 30, the wiring M4 is formed over the interlayerinsulating film IL4, and is coupled to the wiring M3 via the plugs P4.

An interlayer insulating film IL5 is formed over the wiring M4. Theopening OA1 is provided in the interlayer insulating film IL5, and apart of the wiring M4 is exposed from the bottom of the opening OA1. Theexposed portion of the wiring M4 is called the pad region PD1. Thewiring M4 is the wiring containing aluminum.

A rewiring RW is formed in the opening OA1 and over the interlayerinsulating film IL5. Consequently, the wiring M4 and the rewiring RW arecoupled to each other at the bottom (pad region PD1) of the opening OA1.The rewiring RW is the wiring containing aluminum.

In the semiconductor device of the present embodiment, the wiring M4 isthe top-layer wiring, desired wire connection of a semiconductor element(for example, the above-described MISFET) is made by the wirings (M1 toM4), and desired operation can be performed. Consequently, utilizing thepad region PD1, which is the exposed portion of the wiring (top-layerwiring) M4, can be performed a test (a test step) of whether or not thesemiconductor device performs the desired operation.

Additionally, the rewiring RW is the wiring to pull out the pad regionPD1, which is a part of the wiring (top-layer wiring) M4, to a desiredregion (a pad region PD2) of a chip.

A protection film PI is formed over the rewiring RW. An opening OA2 isprovided in the protection film PI, and a main surface of the rewiringRW is exposed from a bottom of the opening OA2. The exposed portion ofthe rewiring RW is called the pad region PD2.

In addition, the projection electrode (bump electrode) BP including theconductive member is formed over the pad region PD2. In addition, abonding wire including a conductive member may be coupled to over thepad region PD2.

Here, in the present embodiment, the aluminum nitride film M4 e isformed on the pad region PD1 (exposed surface) of the wiring (top-layerwiring) M4 containing aluminum, and corrosion of the wiring M4 isprevented. In addition, an aluminum nitride film RWb is formed on thepad region PD2 (an exposed surface) of the rewiring RW containingaluminum, and corrosion of the rewiring RW is prevented.

As described above, also in a case where time is required by theinspection step, the silicon nitride film is formed on the back surfaceof the semiconductor substrate, and where the state of the exposure ofthe pad region PD1 continues for a long period of time, formationreaction of foreign substances can be effectively prevented by formingthe aluminum nitride film M4 e on the pad region PD1. In addition, alsoin a case where time is required by a subsequent step, such as thebonding step, the silicon nitride film is formed on the back surface ofthe semiconductor substrate, and where a state of the exposure of thepad region PD2 continues for a long period of time, formation reactionof foreign substances can be effectively prevented by forming thealuminum nitride film RWb on the pad region PD2.

Next, formation steps of the wiring M4 and the rewiring RW will beexplained.

First, the interlayer insulating film IL5 is formed over the wiring M4.For example, similarly to the case of the first embodiment, a siliconnitride film IL5 a is deposited over the interlayer insulating film IL4including the top of the wiring M4 by the CVD method or the like andfurther, a silicon oxide film IL5 b is deposited over the siliconnitride film IL5 a by the CVD method or the like (refer to FIG. 23).

Next, the opening OA1 is formed by removing the interlayer insulatingfilm IL5 over the pad region PD1 of the wiring M4 (aluminum film M4 b).For example, a photoresist film having an opening in the formationregion of the opening OA1 is formed over the interlayer insulating filmIL5, and the interlayer insulating film IL5 is etched by using thephotoresist film as a mask. Next, the exposed titanium film M4 c isfurther etched. As a result, the aluminum film M4 b of the pad regionPD1 is exposed (refer to FIG. 24).

Next, an aluminum nitride film (AlN film) is formed by nitriding the padregion PD1 of the aluminum film M4 b (refer to FIG. 25). For example,similarly to the case of the first embodiment, ammonia (NH₃) plasmatreatment is performed.

Next, utilizing the pad region PD1, performed is a test of whether ornot the semiconductor device performs desired operation. For example, aprobe needle is stuck into the pad region PD1, and conduction test isperformed. At this time, since a film thickness of the aluminum nitridefilm (AlN film) is several nanometers, the aluminum nitride film can beeasily broken through by the probe needle, and does not interfere withthe conduction test.

Next, the rewiring RW including the conductive film is formed in theopening OA1 and over the interlayer insulating film IL5. For example, analuminum film is deposited in the opening OA1 and over the interlayerinsulating film IL5 as a conductive film using the sputtering method orthe like. A stacked film including a titanium/titanium nitride film, analuminum film, and a titanium nitride film may be used as the conductivefilm. Next, the rewiring RW is formed by patterning the above-describedconductive film using the photolithography technology and the etchingtechnology.

Next, the protection film PI is formed over the rewiring RW. Forexample, a photosensitive polyimide film is used as the protection filmPI, and it is coated over the rewiring RW and the interlayer insulatingfilm IL5.

Next, the opening OA2 is formed by removing the protection film PI overthe pad region PD2 of the rewiring RW (aluminum film RWa). For example,the opening OA2 is formed by exposing and developing the photosensitivepolyimide film. As a result, the rewiring (aluminum film) RW of the padregion PD2 is exposed. It is to be noted that when the stacked filmincluding the titanium/titanium nitride film, the aluminum film, and thetitanium nitride film is used as the rewiring RW, the titanium nitridefilm of the pad region PD2 is also removed, and the aluminum film isexposed.

Next, an aluminum nitride film (AlN film) is formed by nitriding the padregion PD2 of the rewiring (aluminum film) RW. For example, similarly tothe case of the first embodiment, ammonia (NH₃) plasma treatment isperformed.

After that, back grinding of the semiconductor substrate S is performed,the semiconductor substrate S is reduced in film thickness, and is cut(diced) to be divided into a plurality of semiconductor chips (dividedinto individual pieces). As a result, a semiconductor chip is obtainedfrom each chip region of the semiconductor substrate S (semiconductorwafer).

Next, the projection electrode (bump electrode) BP including theconductive member is formed over the pad region PD2 (bonding step). Theprojection electrode (bump electrode) BP can be formed similarly to thefirst embodiment. In addition, a bonding wire may be formed over the padregion PD2 similarly to the first embodiment.

It is to be noted that since the aluminum nitride film (AlN film) overthe pad region PD1 of the wiring M4 is easily cracked (broken) by a filmstress at the time of formation of the rewiring RW, electricalconduction of the wiring M4 and the rewiring RW can be achieved. Inaddition, when a connection resistance between the wiring M4 and therewiring RW is high, the aluminum nitride film (AlN film) over the padregion PD1 of the wiring M4 may be removed before the formation step ofthe rewiring RW.

Hereinbefore, although the invention made by the present inventor hasbeen specifically explained based on the embodiments, the presentinvention is not limited to the above-described embodiments, and it isneedless to say that various changes can be made without departing fromthe scope of the invention.

For example, although the wirings M1 to M3 are formed by patterning inthe first embodiment, they may be formed using a so-called “damascenemethod” in which a conductive film, such as copper (Cu), is buried in awiring groove provided in an interlayer insulating film. In addition,the wirings and the plugs (such as M2 and P2) may be formed using aso-called “dual damascene method” in which the conductive film, such ascopper (Cu), is simultaneously buried in the wiring groove in theinterlayer insulating film and a contact hole thereunder.

What is claimed is:
 1. A semiconductor device comprising: a siliconnitride film formed above a front surface side of a semiconductorsubstrate; a first wiring formed above the silicon nitride film; asecond wiring containing aluminum formed over the first wiring via afirst insulating film; a second insulating film having an opening overthe second wiring; and aluminum nitride formed over the second wiring ata bottom surface of the opening.
 2. The semiconductor device accordingto claim 1, wherein a bonding wire or a bump electrode is formed overthe second wiring at the bottom surface of the opening.
 3. Thesemiconductor device according to claim 1, further comprising: a probemark formed over the second wiring at the bottom surface of the opening.4. The semiconductor device according to claim 1, further comprising:aluminum oxide formed on side walls of the second wiring.
 5. Thesemiconductor device according to claim 4, wherein the aluminum nitrideand the aluminum oxide are formed over the second wiring at the bottomsurface of the opening.
 6. The semiconductor device according to claim1, further comprising: an MISFET formed over the semiconductorsubstrate, wherein the MISFET includes: a gate electrode formed over thesemiconductor substrate via a gate insulating film; and a side wallinsulating film formed on side walls of the gate electrode, and whereinthe silicon nitride film configures the side wall insulating film. 7.The semiconductor device according to claim 1, further comprising: anMISFET formed over the semiconductor substrate; the silicon nitride filmformed over source and drain regions of the MISFET; and a silicon oxidefilm formed over the silicon nitride film.
 8. The semiconductor deviceaccording to claim 1, wherein the semiconductor substrate is in a waferstate, and wherein the silicon nitride film is formed also on a backsurface of the semiconductor substrate.